| 1.2ch 24bit ADC |
| |
64x Oversampling
Sampling Rate up to 96kHz
Linear Phase Digital Anti-Alias Filter
Single-Ended Input
S/(N+D): 90dB
Dynamic Range, S/N: 100dB
Digital HPF for offset cancellation
Overflow flag |
| 2. 6ch 24bit DAC |
| |
128x Oversampling
Sampling Rate up to 96kHz
24bit 8 times Digital Filter
Single-Ended Outputs
On-chip Switched-Capacitor Filter
S/(N+D): 90dB
Dynamic Range, S/N: 106dB
Individual channel digital volume with 256 levels and 0.5dB step
Soft mute
Zero Detect Function |
| 3. 4 inputs 24bit DIR |
| |
| Supports IEC60958 consumer mode, S/PDIF, |
| |
EIAJ CP1201 consumer mode |
Low jitter Analog PLL
PLL Lock Range: 32k ~ 96kHz
Clock Source: PLL or X'tal
4 channel Receivers input and 1 through transmission output
De_emphasis for 32kHz, 44.1kHz and 48kHz
Dedicated Detect Pins |
| |
Non-PCM Bit Stream Detect, DTS-CD Bit Stream Detect,
Validity Flag Detect, 96kHz Sampling Detect,
Unlock & Parity Error Detect, Emphasis Detect, fs change
Detect |
Supports up to 24bit Audio Data Format
Audio I/F: Master or Slave Mode
32bits Channel Status Buffer
Burst Preamble bit Pc, Pd Buffer for Non-PCM bit stream
Master Clock Outputs:128fs/256fs/512fs |
|
| 4. I/F format: MSB justified, LSB
justified(20bit,24bit), I2S or TDM |
| 5. High Jitter Tolerance |
| 6. TTL Level Digital I/F |
| 7. 4-wire Serial and I2C
Bus µP I/F for mode setting |
| 8. Extenal Master Clock Input: |
| |
256fs, 384fs or 512fs for fs=44.1kHz
to 48kHz
128fs, 192fs or 256fs for fs=88.2kHz to 96kHz |
| 9. Power Supply: 4.5 to 5.5V |
| 10. Power Supply for output buffer:
2.7 to 5.5V |
| 11. Small 44pin LQFP |